Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques

2018Access restricted to the OSU Community, at author's request, from 2017-06-27 to 2017-12-27The internet-of-things is a growing market segment which is based on an array\ud of portable communication devices with high power efficiency. Advanced semiconductor\ud technology can easily improve their digital performance, but the same\ud cannot be said for the analog blocks which are vital to their operation. High\ud performance analog circuits continue to use conventional design techniques and\ud architectures at the expense of power efficiency. Deeply scaled CMOS exaggerates\ud this trade-off, opening the door for novel system techniques that take advantage of\ud the digital nature of sub-micron transistors. This research focuses on two highly\ud digital ADCs which can mitigate the short channel effects of limited output swing\ud and low intrinsic gain while also benefiting from process scaling.\ud \ud First, a multi-domain ADC is used to perform quantization on both voltage\ud and time domain signals, relaxing the power-performance trade-off. This hybrid\ud approach can lead to a high resolution, high efficiency data converter in scaled\ud process. A prototype ADC was fabricated in 180nm CMOS, showing an SNDR\ud of 73 dB, operating at 20 MHz sampling frequency, with a power consumption of\ud 1.28 mW.\ud \ud Next, an automated synthesis process is used to automatically generate a high\ud speed VCO-based quantizer from verilog code. Stochastic spatial averaging is\ud combined with a high speed open-loop noise-shaping quantizer to provide enhanced\ud resolution in the presence of device mismatch. Simulation results of a prototype\ud ADC in 180nm CMOS shows an SNDR of 49 dB, operating at 800 MHz sampling\ud frequency and 50 MHz signal bandwidth