Characterizing Defects Responsible for Charge Transport Characteristics at Interfaces of Nano-Thick Materials Stacks

Major functioning blocks in modern devices employed in a variety of applications (electronics, energy harvesting, sensors, etc.) comprise of stacks of nm-thin layers of dielectric materials in contact with conductive electrodes (semiconductors, metals). The performance and reliability of these devices are affected by charge transfer characteristics of these multilayer stacks. We discuss collaboration between electrical measurements and computational modeling leading to identification of defects responsible for degradation phenomena in nm-thin dielectric films employed as gate dielectrics in metal oxide field effect transistors