A New Physical Method Based on CV--GV Simulations for the Characterization of the Interfacial and Bulk Defect Density in High-k/III--V MOSFETs

We propose a new defect characterization technique for high-k dielectric stacks in III-V MOSFETs. This technique allows extracting the defect density from the simulations of the C-V and G-V characteristics at different frequencies. The simulation is performed using a physical distributed compact model, where the trap-assisted capture and emission processes are described in the framework of the multiphonon trap-assisted tunneling theory, including lattice relaxation. The technique, tested on InGaAs MOS devices with different gate-stacks, allows profiling the interfacial and bulk defects in the (E, z) domain. The extracted map, consistent with previous report, allows reproducing C-V and G-V curves on the whole frequency and gate voltage ranges and monitoring the quality of dielectric stacks for the optimization of the manufacturing process