Multi-level energy/power-aware design methodology for MPSoC

International audienceMultiprocessor Systems-on-Chip (MPSoC) are becoming one of the most used solutions in order to meet the growing computation requirements of modern embedded applications. In such systems, power/energy consumption is a critical metric that should be taken into account in the design flow. System designers need an efficient power-aware design methodology and tools to cope with the complexity of MPSoC design. To address this challenge, we present in this paper a power-aware design methodology that relies on multi-level design space exploration. We propose a two-phase exploration process making profit first from functional-level simulations to reduce rapidly and significantly the solution space, and second from transactional-level simulations for better accuracy to select the most appropriate solution. Our methodology uses the same power modeling approach for the MPSoC at both the functional and transactional levels in order to guarantee the coherence of the estimation strategy. Furthermore, our methodology integrates runtime optimization techniques to reduce the energy/power consumption of the system. The efficiency of the proposed power-aware design methodology was demonstrated through a H.264 video decoder case study