Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, such as unit delay, are treated uniformly with combinational gates. Both kinds of gates are functions in a particular topos: the topos of presheaves over the natural ordering of N. This is used to show that sequential circuits validate the equational theory of traced categories. When giving semantics to circuits (typically boolean circuits), it is customary to treat the combinational – i.e. time-independent – parts of the circuits differently from time sensitive ones. Since it is usually assumed that the only time-sensitive gate is the unit delay, each outgoing wire from a delay is considered an additional input, and each incoming wire an add...
This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions sy...
International audienceIn this paper we report some progress in applying timed automata technology to...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, ...
A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in te...
Abstract-It is shown how any combinational function that can in a spatial sequence. Note that both Z...
The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forwar...
AbstractThis article exhibits a particular encoding of logic circuits into a sheaf formalism. The ce...
Transient simulation of a gate circuit is an ecient method of counting signal changes occurring duri...
In three main divisions the book covers combinational circuits, latches, and asynchronous seque...
We suggest the use of a declarative programming language to design and describe circuits, concentrat...
We propose a hierarchical timing analysis technique for combinational circuits under the tightest kn...
Pulse gates have shown promise as a structured manual methodology for the design of high performance...
This paper presents a proof that the adversary path timing assumption is both necessary and suffici...
A Boolean circuit is a collection of gates and wires that performs a mapping from Boolean inputs to ...
This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions sy...
International audienceIn this paper we report some progress in applying timed automata technology to...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, ...
A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in te...
Abstract-It is shown how any combinational function that can in a spatial sequence. Note that both Z...
The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forwar...
AbstractThis article exhibits a particular encoding of logic circuits into a sheaf formalism. The ce...
Transient simulation of a gate circuit is an ecient method of counting signal changes occurring duri...
In three main divisions the book covers combinational circuits, latches, and asynchronous seque...
We suggest the use of a declarative programming language to design and describe circuits, concentrat...
We propose a hierarchical timing analysis technique for combinational circuits under the tightest kn...
Pulse gates have shown promise as a structured manual methodology for the design of high performance...
This paper presents a proof that the adversary path timing assumption is both necessary and suffici...
A Boolean circuit is a collection of gates and wires that performs a mapping from Boolean inputs to ...
This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions sy...
International audienceIn this paper we report some progress in applying timed automata technology to...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...