A high powered radar interference mitigation technique for communications signal recovery with FPGA implementation

In this thesis, we investigate the demodulation of a communications signal that is interfered with by a high-powered radar signal. We choose quaternary phase-shift keying (QPSK) modulation for illustration. The radar phase offset is initially assumed to be fixed. Later, a practical phase sequence is added to the phase offset. A least-squares estimator (LSE) is used to estimate the amplitude and fixed-phase offset of the interfering radar signal to be used for interference cancellation. Then, we utilize a maximum-likelihood detection (MLD) receiver. We show that the QPSK symbol error ratio (SER) improvement in the radar interference depends on collection time. The variance of the estimate increases as the QPSK signal-to-noise ratio (SNR) increases. The increase in variance affects SER. SER results approach the ideal with increasing collection times. For the case where the phase offset includes a phase sequence, the original LSE technique is modified. Later, a system is created in Simulink and converted to hardware-description language (HDL). The SER performance of the HDL implementation in hardware is compared to those of the signal model. SER performance is somewhat degraded in the hardware implementation. [Reprinted in part, with permission, from G. Meager, R.A. Romero, Z. Staples, Estimation and cancellation of high powered radar interference for communication signal collection, in 2016 IEEE Radar Conf., 2016, pp. 1–4, doi: 10.1109/RADAR.2016.7485263.]http://archive.org/details/ahighpoweredrada1094553018Civilian, Raytheon (SAS) CorporationApproved for public release; distribution is unlimited