Chip-Package Interfacial Stress Analysis and Reliability Implications for Flip-Chip Power Devices

The solder in flip-chip assemblies experience high stress and strain because of thermal mismatch induced deformation. These deformations occur because of the differences of coefficient of thermal expansion between flip-chip assembly materials. The similarly in stress profiles between thermal induced and shear induced stress in solder joints enable the use of die shear testing as a representative technique for relating the max stress the flip-chip can withstand to cyclic thermal fatigue failures. In this work, two electronic device sample preparation types are evaluated: One set of samples are soldered together and other set of samples use epoxy as an adhesive. The soldered samples will have different temperature histories to observe how the max stress is affected by operating environments. For the epoxy samples there will be a sensitivity analysis between the adhesive height and temperature change to conclude what effects solder joint stress more. For solder samples, the temperature history (bake time in oven) decreases the max shear stress in the solder but due to sample limitations, knowing exactly how much is still undetermined. For epoxy samples, as temperature change doubles max interfacial and peeling stress doubles. When gap height doubles interfacial stress decreases by 29.29% and peeling stress decreased by 36.23% (traction free boundary) and 29.74% (periodic boundary)