Development of a Massively Parallel Coarse Grained Reconfigurable Fabric verification Environment using Universal Verification Methodology

According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only 120% increase in the power budget and no increase in the design team size to deal with designs that are 10X more complex. One solution to cope with this complexity is to increase the granularity of the building blocks for developing new architectures. As a solution, Dynamically Reconfigurable Resource Array (DRRA) with Distributed Memory Architecture(DiMArch) was developed. As the design complexity increased, the need for verification became inevitable in the design flow. To include the feature of reusability, a reconfigurable verification environment is required to effectively verify the device under test (DUT) and also improve the productivity in the design cycle. The thesis work begins with the specification & design and also the verification plans for the DRRA and DiMArch. The major task of the thesis work is in developing a reconfigurable verification environment for the DRRA using Universal Verification Methodology (UVM) and a systemlevel verification test bench for the DiMArch . This thesis work also focuses on the possible power optimization in the design