An improved instruction-level power and energy model for RISC microprocessors

Recently, the power and energy consumed by a chip has become a primary design constraint for embedded systems and is largely aaffected by software. Because aims vary with the application domain, the best program is sometimes the most power or energy efficient one rather than the fastest. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power without measurement. Therefore, it is vital to discover which factors can affect a program's power and energy consumption.In this thesis we present an instruction level model to estimate the power and energy consumed by a program. Firstly, instead of studying the different instructions individually, we cluster instructions into three groups: ALU, load and store. The power is affected by the percentage of each group in the program. Secondly, the power is affected by the instructions per cycle (IPC) of the program since IPC can reflect how fast the processor runs.There are three advantages of this method, and the first one is conciseness. The reason is that it does not consider the overhead energy as an independent factor or the operand Hamming distance of two consecutive instructions. The second one is accuracy. For example, the errors of our method across different benchmarks with different processors on the development boards are all less than 10%. The last and the most important advantage of this method is that it can apply to different processors, such as OpenRISC processor, ARM11, ARM Cortex-A8, and a dual- core ARM Cortex-A9 processor. We have demonstrated that the previous instruction level power/energy model cannot be extended to superscalar processors and multi-core processors.