A low-voltage high-speed sampling technique

Browse > Conferences> ASIC, 2001. Proceedings. 4th I ... A low-voltage high-speed sampling technique * 982539 abstract Download Citations * Email * Print * Rights And Permissions * Access The Full Text Sign In:Full text access may be available with your subscription User Name Password Forgot Username/Password? Athens/Shibboleth Sign In * Already Purchased * Purchase Now Gang Xu; Yuan, J.; Competence Center for Circuits Design, Lund Univ. This paper appears in: ASIC, 2001. Proceedings. 4th International Conference on Issue Date: 2001 On page(s): 228 - 231 Meeting Date: 23 okt 2001 - 25 okt 2001 Location: Shanghai , China Print ISBN: 0-7803-6677-8 References Cited: 5 INSPEC Accession Number: 7260703 Digital Object Identifier: 10.1109/ICASIC.2001.982539 Date of Current Version: 06 augusti 2002 Abstract A new sampling technique is proposed, which integrates input current instead of tracking input voltage to realize high speed and low voltage sampling. Both the theoretical deduction and the simulation prove the advantages of improving the speed and accuracy of CMOS sampling circuits. A practical charge sampling circuit with 3 V supply, 500 MS/s and 9-bit accuracy is suggested