Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation

The ever expanding market of ultra portable electronic products is compelling the designer to invest major efforts in the development of small and low energy electronic devices. The driving force and benefactors of such devices are (but not limited to) e-health system, sensor network applications, security systems, environmental applications, and home automation systems. These markets have launched a massive trend towards ultra low-energy and ultra low-voltage devices. As the technology scales, the dimensions of a transistors have become extremely small, leading to reliability and process variation issues. Above all, with the ability of placing millions of gates in a small area, high current consumption have become one of the key factors in modern high-performance technologies. In portable electronics, the battery life time is a major issue, as most of the time the device is accompanied with an enclosed battery that has to last for long periods without compromise on performance. Furthermore, there are many applications where the battery lifetime sets the lifetime of the device. Therefore, research is needed to identify the techniques and the impact of them on the design operated for ultra low-energy. The low energy dissipation requirements on a design are achievable by employing various optimization techniques. Voltage scaling is the most effective knob to reduce energy dissipation. For this reason ultra-low energy design usually translates into ultra-low voltage or subthreshold (sub-VT) domain operation. This work presents an analysis on design space for ultra-low energy dissipation of digital circuits. The circuits are operated in the sub-VT region with moderate throughput constraints. The drawback of operating circuits in sub-VT is slow speed performances and reduced reliability. To combat speed degradation due to scaling of the supply voltage, the architectural design space, needs exploration. Techniques such as device sizing, body biasing, stacking transistors, dual threshold gates, multi threshold synthesis, pipelining, and loop unfolding, are explored and applied to the designs. The designs are synthesized in a 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as multi-VT designs. A sub-VT energy model is applied to characterize the designs in the sub- VT domain. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The minimum reliable operation voltage (ROV) for gates in low power 65 nm CMOS technology is found to be around 250 mV. The applied energy model for designs to be characterized for sub-VT domain operation is presented. The energy model encompasses single VT implementations and multi- VT implementations. The energy modeling is based on the 65 nm CMOS standard cells provided by the technology vendor. The energy model has been used to evaluate various techniques and constraints for a circuits operated in the sub-VT domain. The work describes how the energy dissipation of architectures vary w.r.t. switching activity, e. The effects of pipelining together with supply voltage scaling is analyzed, which shows that they have high benefits with respect to energy dissipation. Various half-band digital (HBD) filter structures are evaluated for minimum energy dissipation in the sub-VT domain for a throughput constrained system. All architectures, i.e., unfolded and the basic HBD filter, are implemented and simulated using 65 nm Low-Power High-Threshold (HVT) standard cells. The application of a sub-VT energy model reveals that it is beneficial to use an unfolded implementation to achieve low energy dissipation per sample at EMV, when compared to the energy dissipated by a basic simplified HBD filter implementation. Various available threshold options are analyzed with the help of filter structures by using 65 nm Low-Leakage High-Threshold (HVT), Standard-Threshold (SVT) and Low-Threshold (LVT) standard cells. Secondly, the design space is increased by utilization of a combination of HVT + SVT and also HVT + LVT cells. The analysis with sub-VT energy model leads to the conclusion that a suitable design is a synergy between parallelism, and utilization of various threshold options. In this analysis the multi-VT, implementations did not show a major advantage over single VT implementations. A decimation filter chain consisting of 4 HBD filters is fabricated and the silicon measurements demonstrate that SVT and different architectural flavors are suitable for a ultra low energy (ULE) implementation. Silicon measurements prove functionality down to a supply at 350 mV, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle. Additionally, an alternative to SRAM macro is presented for sub-VT operations. The memory is based on standard-cells and is referred to as SCMs. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT energy characterization model