Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the threshold voltages of nanowire capacitors with different diameter are determined and analyzed using an improved radial metal-insulator-semiconductor field-effect transistor model. This allows for a separation of doping in the core of the nanowire from the surface charge at the side facets of the nanowire. The data show that the doping level in the InAs nanowire can be controlled on the level between 2×1018 to 1×1019 cm−3, while the surface charge density exceeds 5×1012 cm−2 and is shown to increase with higher dopant precursor molar fraction
This thesis aims to show the prospect of capacitance measurements over nanowire arrays as an evaluat...
Since the introduction of the transistor and the integrated circuit, the semiconductor industry has ...
Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel mate...
Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the thr...
Sn and Se dopedInAsnanowires are characterized using a capacitance-voltage technique where the thres...
InAs/HfO2 nanowire capacitors using capacitance-voltage (CV) measurements are investigated in the ra...
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (<...
The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a P...
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (D...
The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a Po...
We fabricate dual-gated electric double layer (EDL) field effect transistors based on InAs nanowires...
We report the growth and characterization of InAs nanowires capped with a 0.5–1 nm epitaxial InP she...
We investigated the transport properties of lateral gate field effect transistors (FET) that have be...
Semiconductor nanowires have emerged as versatile components in superconducting hybrid devices forMa...
We have investigated the scaling properties of [111] InAs nanowire MOSFETs in the ballistic limit. T...
This thesis aims to show the prospect of capacitance measurements over nanowire arrays as an evaluat...
Since the introduction of the transistor and the integrated circuit, the semiconductor industry has ...
Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel mate...
Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the thr...
Sn and Se dopedInAsnanowires are characterized using a capacitance-voltage technique where the thres...
InAs/HfO2 nanowire capacitors using capacitance-voltage (CV) measurements are investigated in the ra...
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (<...
The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a P...
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (D...
The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a Po...
We fabricate dual-gated electric double layer (EDL) field effect transistors based on InAs nanowires...
We report the growth and characterization of InAs nanowires capped with a 0.5–1 nm epitaxial InP she...
We investigated the transport properties of lateral gate field effect transistors (FET) that have be...
Semiconductor nanowires have emerged as versatile components in superconducting hybrid devices forMa...
We have investigated the scaling properties of [111] InAs nanowire MOSFETs in the ballistic limit. T...
This thesis aims to show the prospect of capacitance measurements over nanowire arrays as an evaluat...
Since the introduction of the transistor and the integrated circuit, the semiconductor industry has ...
Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel mate...