A Noise Cancelling 0.7-3.8 GHz Resistive Feedback Receiver Front-End in 65 nm CMOS

This paper presents a noise cancelling 0.7– 3.8GHz receiver front-end implemented in 65nm technology. The circuit has a main path consisting of a high input impedance gm-stage, current-mode passive mixers and baseband amplifiers, where the input match is provided by frequency translational negative feedback from baseband to RF input. An auxiliary path with tunable gain is introduced to cancel noise from the main path while maintaining linearity. The receiver front-end achieves a noise figure of 1.6–3.7dB and an IIP2 and IIP3 of >75dBm and >1dBm, respectively. The current consumption of the circuit is 22.8–34.9mA, from a 1.2V supply