Vertical Nanowire High-Frequency Transistors

This thesis explores a novel transistor technology based on vertical InAs nanowires, which could be considered both for low-power high-frequency analog applications and for replacing Si CMOS in the continued scaling of digital electronics. The potential of this device - the vertical InAs nanowire MOSFET – lies in the combination of the outstanding transport properties of InAs and the improved electrostatic control of the gate-all-around geometry. Three generations of the vertical InAs nanowire MOSFET are presented in this thesis; the first generation, integrated on semi-insulating InP substrate, provided the first RF measurements on vertical nanowire transistors with extrinsic ft/fmax > 7/20 GHz. Utilizing the resilience towards dislocations inherent to the vertical nanowire growth, the second generation is integrated on highly resistive Si substrates by a thin InAs buffer layer. The RF performance is comparable to the first generation, indicating sustained crystal quality of the nanowires. In the third generation, however, a great boost in the RF performance is achieved by removing excess metal overlap and, hence, reducing the parasitic gate capacitance, which resulted in extrinsic ft/fmax = 141/155 GHz at Lg ≈ 150 nm. The main challenge for III-V MOSFETs is the high-κ integration as high densities of charge traps deteriorate the device performance. Focusing on the border traps, a method based on frequency dispersion in gm (1 Hz-100 GHz) is developed for direct measurement of the trap density as a function of distance from the oxide-semiconductor interface. The method is demonstrated for vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs