Impact of distributed directories on performance of wireless network-on-chip architectures

Presented to the 13th Annual Symposium on Graduate Research and Scholarly Projects (GRASP) held at the Rhatigan Student Center, Wichita State University, April 28, 2017.Research completed in the Department of Electrical Engineering and Computer Science, College of EngineeringMulticore architectures are expected to integrate hundreds of processing cores in the near future. Dynamic cache behavior is a major drawback in improving scalability and performance of multicore network-on-chip (NoC) architectures. Wireless NoC (WNoC) has been proposed as a promising solution to enhance multicore performance. We previously introduced a centralized directory (CD) in WNoC to reduce the communication latency. In this work, we proposed distributed directories (DDs) in WNoC along with an adaptive minimal routing algorithm that allowed the architecture to perform faster. The proposed WNoC architecture with 36 nodes and four DDs is modeled and simulated using VisualSim tool and synthetic workload. The simulation results showed that the communication latency due to the proposed WNoC-DDs is reduced up to 15.60% and 5.40% when compared with those due to WNoC and WNoC-CD, respectively. On average, the proposed WNoC-DDs helped save more power consumption when compared with WNoC and WNoC-CD.Graduate School, Academic Affairs, University Libraries, Regional Institute on Agin