In Part I of this paper, a larger asynchronous circuit was regarded as successfully simulating a smaller one if the former was a “good extension” of the latter, and the adverse effects of the delays on the inter-element wires, i.e., the delay problem, was investigated from this viewpoint. A closer examination made here, however, reveals that a good extension is usually insufficient for a truly successful simulation, and that a larger circuit must be “spike-free” in addition to being good. Accordingly, the delay problem is reinvestigated from this new viewpoint. Also, some relationships are established between good and spike-free extensions. An important result is that a spike-free delay network incorporation having binary wires only is a go...
AbstractWe consider the problem of synthesizing the asynchronous wrappers and glue logic needed for ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC netw...
AbstractDelays of signal propagation inherent in the wires interconnecting the logical elements of a...
Although the theory of asynchronous circuits (fates back to the early 1950s, considerable progress h...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Consider a network N constructed from a set of modules interconnected by wires. Suppose that there i...
ISBN 2-84813-029-6ITRS 2003 forecasts importance of asynchronous digital design style growth with di...
Abstract. The study of asynchronous circuit behaviors in the presence of component and wire delays h...
Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating del...
A delay circuit is a circuit which produces rectangular pulses of specified duration. A rectangular ...
Two trends are of major concern for digital circuit designers: the relative increase of interconnect...
This paper presents a general method for designing delay insensitive datapath circuits. Its emphasis...
Transient simulation of a gate circuit is an ecient method of counting signal changes occurring duri...
AbstractWe consider the problem of synthesizing the asynchronous wrappers and glue logic needed for ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC netw...
AbstractDelays of signal propagation inherent in the wires interconnecting the logical elements of a...
Although the theory of asynchronous circuits (fates back to the early 1950s, considerable progress h...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Consider a network N constructed from a set of modules interconnected by wires. Suppose that there i...
ISBN 2-84813-029-6ITRS 2003 forecasts importance of asynchronous digital design style growth with di...
Abstract. The study of asynchronous circuit behaviors in the presence of component and wire delays h...
Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating del...
A delay circuit is a circuit which produces rectangular pulses of specified duration. A rectangular ...
Two trends are of major concern for digital circuit designers: the relative increase of interconnect...
This paper presents a general method for designing delay insensitive datapath circuits. Its emphasis...
Transient simulation of a gate circuit is an ecient method of counting signal changes occurring duri...
AbstractWe consider the problem of synthesizing the asynchronous wrappers and glue logic needed for ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC netw...