AbstractIn this paper we consider shared-memory switches. We introduce a novel general non-preemptive buffer management scheme, which considers the queues ordered by their size. We propose a new scheduling policy, based on our general scheme, which we call the Harmonic policy. We analyze the performance of the Harmonic policy by means of competitive analysis and demonstrate that its throughput competitive ratio is at most ln(N)+2, where N is the number of output ports. We also present a lower bound of Ω(logN/loglogN) on the performance of any online deterministic policy. Our simulations also show that the Harmonic policy achieves high throughput and easily adapts to changing load conditions
This paper considers the problem of packet-mode scheduling of input queued switches. Packets have va...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
The growth of today’s Internet has been constrained substantially by the performance of interconnect...
We consider the Longest Queue Drop memory management policy in shared-memory switches consisting of ...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
An efficient self-adaptive packet queueing policy, called Queueing with Output Address Grouping (QOA...
Input queued (IQ) switches are highly scalable and they have been the focus of many studies from aca...
We consider the problem of managing the buffer of a shared-memory switch that transmits packets of u...
Combined input and output queued (CIOQ) architectures with a moderate fabric speedup S > 1 have c...
A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing thi...
In this work, we study the problem of buffer management in network switches from an algorithmic pers...
Abstract—Scheduling algorithms for input-queued packet switches have been widely researched. It has ...
In this dissertation, we develop and analyze algorithms for scheduling in input-buffered switch fab...
We consider a switched (queuing) network in which there are constraints on which queues may be serve...
The online buffer management problem formulates the problem of queueing policies of network switches...
This paper considers the problem of packet-mode scheduling of input queued switches. Packets have va...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
The growth of today’s Internet has been constrained substantially by the performance of interconnect...
We consider the Longest Queue Drop memory management policy in shared-memory switches consisting of ...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
An efficient self-adaptive packet queueing policy, called Queueing with Output Address Grouping (QOA...
Input queued (IQ) switches are highly scalable and they have been the focus of many studies from aca...
We consider the problem of managing the buffer of a shared-memory switch that transmits packets of u...
Combined input and output queued (CIOQ) architectures with a moderate fabric speedup S > 1 have c...
A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing thi...
In this work, we study the problem of buffer management in network switches from an algorithmic pers...
Abstract—Scheduling algorithms for input-queued packet switches have been widely researched. It has ...
In this dissertation, we develop and analyze algorithms for scheduling in input-buffered switch fab...
We consider a switched (queuing) network in which there are constraints on which queues may be serve...
The online buffer management problem formulates the problem of queueing policies of network switches...
This paper considers the problem of packet-mode scheduling of input queued switches. Packets have va...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
The growth of today’s Internet has been constrained substantially by the performance of interconnect...