Low voltage adiabatic flip-flops based on power-gating CPAL circuits

AbstractThis paper presents low voltage adiabatic flip-flops with power-gating techniques. The flip-flops are realized by CPAL (Complementary Pass-Transistor Adiabatic Logic) circuits with DTCMOS (Dual Threshold CMOS) techniques. The designs of adiabatic sequential circuits with power-gating techniques are described. Voltage scaling for power-gating adiabatic mode-8 counter is verified. All circuits are simulated using NCSU PDK 45nm technology by varying supply voltages. Based on the simulation results, the power-gating DTCMOS adiabatic flip-flops that operate on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions