Performance of Clock Mesh Under Dynamic Voltage and Frequency Scaling

AbstractMesh based clock distribution is gaining popularity in microprocessor based designs, because of its tolerance to skew induced by process variations in Deep Sub-Micron technologies (DSM). In the recent past, there has been much research on reduction of power consumed by any chip and Dynamic Voltage and Frequency Scaling (DVFS) has emerged as one of the prominent methods for reducing the power. In this work, we first synthesize a capacitance driven clock mesh and study the variations of skew when the mesh is operated under a DVFS technique. Based on the observations, a novel method to reduce the skew variations is then proposed