A Novel Phase Frequency Detector for a High Frequency PLL Design

AbstractA simple new phase frequency detector (PFD) is presented in this paper. This PFD use only 10 transistors, whereas a conventional PFD uses 54 transistors. It has been observed that the proposed PFD could operate up to frequencies about 4.6 times higher than that by conventional PFD. It has also been observed that the power dissipation is reduced by 99%. In addition to these, area of the circuit has been reduced up to 73% when compared with conventional PFD. The phase noise of designed PFD has been reduced to - 133.4 dBc/Hz. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK090 library of 180nm technology with a supply voltage of 1.8V. The reset process has been completely removed in this design thereby eliminating the blind zone and speeding up the acquisition process. The design has been proposed for high speed, low power and low jitter applications