Datapath Design and Full Custom Implementation of Radix-2 CORDIC Processor

AbstractThe CORDIC algorithm can be implemented efficiently for trigonometric computing which is important in image processing, navigation. And a full custom implementation has better performance in low silicon area and high throughput. This paper presents a 32 bits full custom layout design for CORDIC architecture by using pipelining techniques to increase the throughput of the processor. As a result, the area of CORDIC data-path is 6.0μm2 in the SIMC 0.13μm 1P8M CMOS process. The critical path delay is 0.639ns at the Typical-Typical corners(Voltage 1.2V Temperature 25°C), wire delay which approximates twice or three times as the critical path delay should be added in practice that means the frequency can reach 391MHz approximately