AbstractA VLSI computation model is presented with a time dimension in which the concept of information transfer is made precise and memory requirements (lower bounds for A) and area-period trade-offs (lower bounds for AP2) are treated uniformly. By employing the transitivities of cyclic shiftings and binary multiplication it is proved that AP2α = ω((min(mn, mp, np)l)1 + α), 0 ⩽5 α ⩽ 51, for the problem of multiplying m × n and n × p matrices of l-bit elements. We also show that min(mn, mp,np)l is the exact bound for chip area
Abstract. A new model of computation for VLSI, based on the assumption that time for propagating inf...
This paper initiates the study of communication complexity when the processors have limited work spa...
AbstractArea-time optimal VLSI division circuits are described for all computation times in the rang...
AbstractTwo models for very-large scale integrated (VLSI) semiconductor circuits are considered that...
AbstractChip area and computation time are the resource parameters of greatest importance in VLSI al...
AbstractOn any general sequential model of computation with random-access input (e.g., a logarithmic...
The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of com...
Abstract—Although many efficient high-level algorithms have been proposed for the realization of Mul...
AbstractAn area-universal VLSI circuit can be programmed to emulate every circuit of a given area, b...
Some level-2 and level-3 Distributed Basic Linear Algebra Subroutines (DBLAS) that have been impleme...
We present lower bounds on the amount of communication that matrix multiplication algorithms must pe...
AbstractThe numbers of bit operations (bt) required for matrix multiplication (MM), matrix inversion...
Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and...
The established methodologies for studying computational complexity can be applied to the new proble...
An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at th...
Abstract. A new model of computation for VLSI, based on the assumption that time for propagating inf...
This paper initiates the study of communication complexity when the processors have limited work spa...
AbstractArea-time optimal VLSI division circuits are described for all computation times in the rang...
AbstractTwo models for very-large scale integrated (VLSI) semiconductor circuits are considered that...
AbstractChip area and computation time are the resource parameters of greatest importance in VLSI al...
AbstractOn any general sequential model of computation with random-access input (e.g., a logarithmic...
The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of com...
Abstract—Although many efficient high-level algorithms have been proposed for the realization of Mul...
AbstractAn area-universal VLSI circuit can be programmed to emulate every circuit of a given area, b...
Some level-2 and level-3 Distributed Basic Linear Algebra Subroutines (DBLAS) that have been impleme...
We present lower bounds on the amount of communication that matrix multiplication algorithms must pe...
AbstractThe numbers of bit operations (bt) required for matrix multiplication (MM), matrix inversion...
Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and...
The established methodologies for studying computational complexity can be applied to the new proble...
An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at th...
Abstract. A new model of computation for VLSI, based on the assumption that time for propagating inf...
This paper initiates the study of communication complexity when the processors have limited work spa...
AbstractArea-time optimal VLSI division circuits are described for all computation times in the rang...