Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

AbstractIn order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features; while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness