Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation of combinational circuits is presented. The proposed framework is divided in two stages. First, signal probabilities are computed via a hybrid approach combining heuristics and selective simulation of reconvergent subnets. In the second stage, signal probabilities are used to compute the vulnerability of all the gates in a combinational block using a backward-traversing algorithm that takes into account logical, electrical and timing masking factors. Experimental results show that our signal probability estimation approa...
In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of K...
Integrated circuits are increasingly susceptible to uncertainty caused by soft errors, inherently pr...
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have becom...
Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the in...
We develop a simple model that computes the probability that a strike at the output of a gate has an...
Abstract — Accurate electrical masking modeling represents a significant challenge in soft error rat...
Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increas...
International audienceTechnology scaling in modern electronic circuits shrinks the transistor size a...
Reliability of VLSI circuits had always been a major issue during the design process. It becomes mor...
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for d...
Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital syste...
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced tra...
Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptibl...
We present a soft error rate (SER) analysis methodology within a simulation and design environment t...
In recent years, soft errors happen in the combinational logic circuits that genuinely impact the ac...
In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of K...
Integrated circuits are increasingly susceptible to uncertainty caused by soft errors, inherently pr...
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have becom...
Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the in...
We develop a simple model that computes the probability that a strike at the output of a gate has an...
Abstract — Accurate electrical masking modeling represents a significant challenge in soft error rat...
Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increas...
International audienceTechnology scaling in modern electronic circuits shrinks the transistor size a...
Reliability of VLSI circuits had always been a major issue during the design process. It becomes mor...
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for d...
Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital syste...
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced tra...
Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptibl...
We present a soft error rate (SER) analysis methodology within a simulation and design environment t...
In recent years, soft errors happen in the combinational logic circuits that genuinely impact the ac...
In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of K...
Integrated circuits are increasingly susceptible to uncertainty caused by soft errors, inherently pr...
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have becom...