New feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate conventional monolithic processor designs. On the one hand, exploiting instruction level parallelism is leading us to diminishing returns and therefore exploiting other sources of parallelism like thread level parallelism is needed in order to keep raising performance with a reasonable hardware complexity. On the other hand, clustering architectures have been widely studied in order to reduce the inherent complexity of current monolithic processors. This paper studies the synergies and trade-offs between two concepts, cluster...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domai...
This thesis is concerned with hardware approaches for maximizing the number of independent instructi...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
To maximize the performance of wide-issue superscalar out-of-order microprocessors, the issue stage ...
To maximize the performance of wide-issue superscalar out-of-order microprocessors, the issue stage ...
Journal ArticleClustered microarchitectures are an attractive alternative to large monolithic super...
Different applications may exhibit radically different behaviors and thus have very different requir...
Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-l...
Li, XiaomingWith the Dennard Scaling law break for a long time, the computer architecture design pro...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
Different applications may exhibit radically different behaviors and thus have very different requir...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domai...
This thesis is concerned with hardware approaches for maximizing the number of independent instructi...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
To maximize the performance of wide-issue superscalar out-of-order microprocessors, the issue stage ...
To maximize the performance of wide-issue superscalar out-of-order microprocessors, the issue stage ...
Journal ArticleClustered microarchitectures are an attractive alternative to large monolithic super...
Different applications may exhibit radically different behaviors and thus have very different requir...
Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-l...
Li, XiaomingWith the Dennard Scaling law break for a long time, the computer architecture design pro...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
How to effectively use the increasing number of transistors available on a single chip while avoidin...
Different applications may exhibit radically different behaviors and thus have very different requir...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domai...
This thesis is concerned with hardware approaches for maximizing the number of independent instructi...