Performance evaluation of a storage model for OR-parallel execution of logic programs

As the next step towards a computer architecture for parallel execution of logic programs we have implemented four refinements of the basic storage model for OR-Parallelism and gathered data about their performance on two types of shared memory architectures, with and without local memories. The results show how the different properties of the implementations influence performance, and indicate that the implementations using hashing techniques (hash windows) will perform best, especially on systems with a global storage and caches. We rise the question of the usefulness of the simulation technique as a tool in developing new computer architectures. Our answer is that simulations can not give the ultimate answers to the design questions, but if only the judiciosly chosen parts of the machine are simulated on a detailed level, then the obtained results can give a very good guidance in making design choice.Also located in the Proceedings of the 1986 Symposium on Logic Programming, September 22-25, 1986, Salt Lake City, Utah. pp. 246-257. IEEE Computer Society Press. Original report number R86003.