Evaluatie van instelpunt-temperatuur-instabiliteiten en zelf-geïnduceerde hitte-effecten in geavanceerde halfgeleider technologieën

In order to meet the specifications in terms of drive current and electrostatic channel control of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFET), scaling of the equivalent oxide thickness (EOT) is essential. However, with EOT scaling down to dimensions of only a few atomic layers, the reliability of these dielectrics start to become an issue. One of the main MOSFET degradation phenomena is Bias-Temperature-Instability (BTI), which has evolved in a way that the industry’s reliability targets can no longer be met with planar devices. In order to maintain electrostatic control without scaling EOT, recently 3D device architectures such as FinFETs and gate-all-around nanowires (GAA NW) were introduced. These geometric modifications raised concern over device self-heating effects (SHE). Moreover, in future technologies, completely new channel materials with high carrier mobility will be utilized. In this Thesis, we study the BTI reliability by developing a new technique that allows us to quickly screen the effect of tuned process parameters on the BTI resilience of sub-nm EOT dielectrics. Using the gathered information from systematic benchmarking, we have strong indications that the oxide scavenging technique used to form these UT-EOT devices, also inherently forms a fundamental obstacle for BTI reliability because of the defects generated during this processing. We find that the defectivity and the BTI reliability can be improved by modifying the annealing techniques. Subsequently, more fundamental understanding of BTI-induced oxide defects is provided and by studying its co-interaction with failure mechanisms such as Random-Telegraph-Noise (RTN) and Stress-Induced-Leakage Current (SILC). We demonstrate how gate leakage and fluctuations and charge trapping are related and show that the multi-state non-radiative multi-phonon (NMP) theory can be applied to explain the defect properties. Thereafter, we develop a measurement methodology to quantify the SHE in planar, FinFET and GAA-NW FETs. The technique is corroborated with electro-thermal simulations, uncovering the asymmetric heating of the device. We propose simulations using thermal conductivity tensors to superseed the underlying phonon scattering physics and also review the impact in circuits. Finally, concerning future device nodes with high mobility channels, we find that introducing non-dilute alloys, for example to enhance strain in pFET devices, has a strong impact on the SHE.Chapter 1: Introduction Chapter 2: Overview of failure mechanisms Chapter 3: Characterizing BTI-reliability in ultra-thin EOT devices Chapter 4: Unifying RTN, BTI and SILC in nanoscale devices Chapter 5: Assessing self-heating effects in scaled MOSFET nodes Chapter 6: Self-heating considerations for future technology nodes Chapter 7: Conclusions and perspectivesnrpages: 291status: publishe