Timing calibration for up-converting DAC

This thesis deals with the timing error problem that appears in high frequency Digital to Analog Converters. Inequalities among signal paths in different branches and inaccuracies happened during fabrication, result in different time delays in different branches of a Digital to Analog Converter. The consequence of this inequality is having the data for different bits not arriving to the summation point at the same time. This timing error will create some glitches in the output analog signal. A new approach is introduced in this work that measures the timing error among branches of the DAC and corrects them through a calibration process. Being all the error measurement and its correction process done on chip, this approach can correct the errors created by both sources. This idea was implemented and tested in Eldo simulator. A timing error of 8pS was inserted to the MSB branch of a 10-bit binary coded DAC. After performing the calibration process on this DAC, the SFDR of the output signal was increased by about 3.2dB