Circuit Design and Modeling Techniques of On-chip Power Delivery Modules

University of Minnesota Ph.D. dissertation.January 2015. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); viii, 86 pages.Designing an efficient power delivery network is one of the most important aspects of modern low-power microprocessor designs. Power delivery network consists of off-chip converters, wires/bumps to route power and ground signals from off-chip converters to inside the chip, on-chip converters, and on-chip power grid. Parasitic resistance and inductance of routing wires and package cause IR noise and resonant supply noise in the supply line, whereas parasitic capacitance of the power and ground lines results in a significant increase in the charging and discharging time of the supply lines during transients of dynamic voltage and frequency scaling (DVFS). DVFS, which scales supply voltage depending on the performance requirement of the processor, thereby saving dynamic power dissipation, has become an integral part of today's microprocessor. However, because of large IR noise to route off-chip power and ground signals and large off-chip component count, per-core DVFS in a many-core processor cannot be supported with off-chip converters. We present design techniques to tackle non-idealities of the power delivery networks. At the same time, we propose on-chip power delivery solutions. We present a circuit technique based on staggering activation of cores in order to mitigate first-droop noise from the supply network. From our 65nm bulk CMOS test-chip, we measure a 12.7% improvement in resonant supply noise of a 2-core processor using our proposed noise reduction technique. In order to reduce IR noise of the power delivery network, we propose a switched capacitor step-up converter. The converter built in 32nm SOI CMOS process shows a 45% improvement in IR noise of the supply line. For faster charging of the supply line, we build a step-down converter in 32nm SOI CMOS process, and measured 5x reduction in the charging time of the supply network. Using a 32nm SOI CMOS process, we build an on-chip switched capacitor DC/DC converter, capable of supporting two outputs with the help of time division demultiplexing. Finally, we propose two power delivery system using two industry-standard state-of-the-art power delivery units (fully integrated voltage regulators and low dropout regulators), and compare the power consumption of the entire system using random and minimum power scheduling techniques