An Innovated Design of 60-120V Sided-Isolation NLDMOS with Bench marked Ron for 0.35um CMOS Compatible Process and Hot Carrier Injection (HCI) Reliability Study

[[abstract]]Sided-Isolation NLDMOS: In intelligent power IC’s, it is very important to get a high breakdown with lowest possible specific on-resistance (Rsp) so as to keep heat dissipation as low as possible and thereby enhancing efficiency and reliability. The conventional LDMOS structure still produces high Rsp due to the drift length limit. The newly invented device structure using a very short drift length with Sided-Isolation can deliver the world benchmark Rsp performance, hence the device can have high efficiency and good reliability performance. So in our new innovated design we invented a good idea that the use of Sided-Isolation technique and it will help to keep Rsp very low keeping breakdown still good. N-blanket implantation help to get the low NPN beta and this intern helps to get better On-State IV performance that is enhanced on-state breakdown as one of the SOA parameters. Added PBL implantation beneath the P-body area helps to get rid of Kirk effect problem in on-state family curves. So by using these new innovative techniques we can have optimized the device and we have achieved higher breakdown voltage and world benchmarked Ron. The main difficult to get NPN beta less than 1 so that we can able to achieve good On-state performance with best Rsp also. This Sided-Isolation technique helped us to achieve benchmark Rsp performance without compromising the Off-sate breakdown. Hence, with all these performances this device becomes a good solution for smart power applications. The proposed multiple RESURF LDMOS is able to achieve a benchmark specific on-resistance while maintaining a breakdown voltage and additionally to achieve better ESOA performance. The key feature of this novel device is linear p-top rings which are located on the surface of n-drift region. Optimization of p-top mask design and n-drift region is performed in order to achieve benchmark on-resistance with the desired breakdown voltage. Hot Carrier Injection (HCI) Reliability Test: In long time reliability test of the device, the Hot Carriers those gains extra kinetic energy will trap into the silicon/silicon-di-oxide interface and cause Rsp and Idsat degradation. This mechanism we simulated and tested by using TCAD Sentaurus tool. We used appropriate models to simulate phenomena of charge trapping and degradations that take place in real silicon processes Hot Carrier Injection (HCI) is a mechanism that can generate an interface trap in the Si/SiO2 interface of the MOSFET device. The Generated interface trap will shift the device parameter and degrade its performance.As the device experience high electric field, carrier either electron for NMOSFET or hole for PMOSFET gain high kinetic energy so called hot carrier. This hot carrier will degrade on-resistance and saturation drain current of the device.Hot carrier injection degradation seems to be more significant on NMOSFET because the electron has a lower effective mass compare to hole so that it can gain more kinetic energy from the channel electric field. We perform HCI reliability test for 60V Sided-Isolation NLDMOS device we have measured Id current degradation @vg=5v, Vd=0.1v and Idsat degradation @Vdd=40V and Vg=5v and stress for time 1e3, 1e4, 1e5,1e6,6.93e6 seconds and measure corresponding Idsat and Rsp . Hence we can then know and calculate percentage Rsp and Idsat shift. This shift is due to Hot carriers that trapped into the Si/Sio2 interface region The New Innovated Sided isolation NLDMOS device design has poor HCI performance when we use STI Isolation.The STI isolation is generally used instead of LOCOS isolation due to the device size consideration. The STI can save the space and deliver the same isolation, but in less space. In our study of newly developed side-isolation LDMOS device structure, we have found the STI has a poor performance in the HCI life time test. STI may cause HCI issues due to high field at trench edges. We have found that after 1e4 seconds stress time Idsat Degradation is 15%. However, this new Sided-Isolation device has demonstrated with LOCOS can not only a better HCI improvement which can implement LOCOS by keeping the same drift region, and device size.We have found that after 6.93e6 seconds (0.22Years) stress time Idsat Degradation is only 0.47%. We plot and show the trap charges distribution along the interfaces and these trap charges are more with more stres