Add to ORKGInternational audienceThis paper presents a methodology to synthesize testable circuits in a High-Level Synthesis environment using a graph-based approach. The complexity of the algorithm involved in the proposed approach is of the order O(N), where N is the number of vertices and edges in the graph
In this paper we present a new method for high-level synthesis that enhances design flexibility, spe...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit...
A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each blo...
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate e...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
A high level synthesis for testability method is presented with the objective to generate testable r...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
It is well known that optimal logic synthesis can ensure fully testable combinational logic designs....
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
A method to find hard logic synthesis examples with known upper bound is presented. The circuits can...
In this paper we present a new method for high-level synthesis that enhances design flexibility, spe...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit...
A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each blo...
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate e...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
A high level synthesis for testability method is presented with the objective to generate testable r...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
It is well known that optimal logic synthesis can ensure fully testable combinational logic designs....
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
A method to find hard logic synthesis examples with known upper bound is presented. The circuits can...
In this paper we present a new method for high-level synthesis that enhances design flexibility, spe...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call...