Rapid prototyping of an ATM traffic control algorithm

International audienceThis paper studies the design and rapid prototyping of an ATM-TC (ATM Traffic Controller). We propose a traffic control algorithm using feedback cells carrying VC parameters in order to respect QoS and minimize cell loss. The main objective of this controller is the shaping of bit rate traffics and buffer management based on a linked list scheme allowing optimal use of memories. The circuit fits in several ATM system configurations and will be mainly used at the User-Network or Network-Network Interfaces. This Integrated Circuit was designed with a high level Top-Down methodology using VHDL. A prototype was explored with FPGAs, in order to validate the RTL description, then was realized on a 0.6 µm ?CMOS technology. The Chip is pad limited and is encapsulated on a 208 Package. The circuit complexity is 30 Kgates and its working frequency is 80 MHz