IC thermal map from digital and thermal simulations

International audienceAs the feature size decrease with each process generation, and nominal SoC design size approaching millions of gates, there is a need to explore more in depth the power distribution across the IC and investigate the power planning and thermal effects on the functionality and reliability. We propose in this paper a methodology that allows computing the local power of a digital circuit mapped to the physical representation in order to analyze the power distribution. This is used as inputs to a thermal simulator for extracting the thermal maps of the chip. The power calculation cannot be done at the transistor level for multi-million transistors with large test-benches, otherwise it will need unreasonable CPU resources and memory. This is why the proposed method is based on the digital model, as it is used currently in industry for functional and timing simulations sign-off. The obtained thermal results are accurate accordingly. And this allows both quantitative and qualitative analysis of the thermal behavior under real application inside the circuit