Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

International audienceIn this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multipleparallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derivecomputes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematicalmodel of the multi-level bus arbitration policy used by the MPPA. Further, we refine the analysis to account for therelease dates and response times of co-runners, and the use of memory banks. Further improvements to the precision ofthe analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accessesin the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on anavionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads toresponse times that are a factor of 4.15 smaller for this application, than the default approach of assumingworst-case interference on each memory access