Lightweight Task Migration in Embedded Multi-Tiled Architectures Using Task Code Replication

International audienceWith such ongoing sophistication in embedded applications, higher computational powers are becoming more required. As a result, a wide transition to multi-processor system on chip has been adopted. Our study focuses on fully distributed memory MPSoC which is implemented in multi-tiled architecture. A tile contains at least one processor and associated peripherals with a distributed network processor which is responsible for inter-tile communications. All tiles are connected in a 3D torus network. In this paper, we present a solution for a lightweight task migration on such architectures. It is based on wise task code replication in statically chosen locations (tiles). It provides the system with the ablility to remap its tasks at runtime. This work emphasizes on solving all issues arising from communication inconsistency shedding the light on implementation details. Experiments show the effectiveness of the approach, and detail performances and limitations. The solution has been implemented on a multi-tiled virtual ARM-CortexA9 based platform with an embedded operating system