Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications

International audienceThis paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed high- performance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in! the order of 12 bits and 80 Msps of sampling frequency