An innovative compilation tool-chain for embedded multi-core architectures

In this paper, we propose a compilation tool-chain supporting the eective exploitation of multi-core architectures oering hundreds of cores. The tool-chain leverages on both the application requirements and the platform-specic features to provide developers with a powerful parallel-programming environment able to generate ecient parallel code. The design of parallel applications follows a semi-automatic approach enabling the programmer to transfer to back-end tools platform-specic code generation and optimization, thus making possible to avoid the clobbering of code with non-portable and complex directives. The programmer can graphically parallelize the application (mainly data-streaming ones) for the target platform using Thales' Spear Design Environment. The resulting parallelization is generated under the form of an Intermediate Representation, which is then passed to the back-end tools (HPC Project's Par4All) that generates efficient target code. We present the results obtained parallelizing a small subset of the RT-STAP radar algorithm and the Chirp filltering algorithm on standard multi-core and on nVidia GPUs