Associative memory design for fast tracker at LHC2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)

We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs and improves the functionality for the Fast Tracker (FTK) proposed to upgrade the ATLAS trigger at LHC