Formal approaches to SEUs testing in FPGAs

Various formal approaches can be used to study FPGA-based systems in relationships to faults, in particular to SEUs. Formal approaches, such as high-order logic, model checking, or Stochastic Activity Networks, have been used for fault simulation, analysis of (un)testability, and test pattern generation. This paper reports on experiences and future developments related to soft errors in the configuration memory of SRAM-based devices, which are of particular interest for reconfigurable systems