VLSI Design of a Scheduler to Support Quality of Service in IP Networks

The new emergent network applications such as, voice over IP (Internet Protocol), video streaming, multimedia and interactive video conferencing require a bound on network performance. The scheduling algorithm at the switching nodes plays a critical role in controlling the interaction among different traffic streams. In this paper we present the architecture and the VLSI design of a scheduler to support Quality of Service (QoS) in IP networks using the SSPFQ (Shaped Starting Potential-Based Fair Queuing) scheduling discipline. The proposed SSPFQ scheduler has been designed for a 0.18m CMOS technology for the example case of 32 queues and 128 elements per queue. A complexity of about 138 Kgates for a maximum operating frequency of 100 MHz has been achieved