A NUCA model for embedded systems cache design

Future embedded applications will require high performance processors integrating fast and low-power cache. Dynamic Non-Uniform Cache Architectures (DNUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely Triangular D-Nuca Cache, to reduce power consumption and silicon area occupancy of D-Nuca cache. We compare the performances of Triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of halfsized NUCA cache with performance improvements