A new space Digital Signal Processor design

The increasing demand of on-board real-time processing represents one of the critical issues in forthcoming scientific and commercial European space missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications, especially due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations restrictions (ATMEL TSC21020) faces a poor performance of 60 MFLOPs peak, and it is becoming inadequate to fulfill the computation demand of the space missions. For this reason, the development of a new generation of space-qualified DSP is well known in the European space community. The space-qualified DSP architecture proposed in this work fills the gap between the computational requirements and the available devices. Additionally, it has been implemented using technologies available in Europe without any restriction. The DSP processor leverages a pipelined and massively parallel core based on the Very Long Instruction Word paradigm, with 64 registers and 8 operational units. The rest of the System-on-Chip architecture consists in the instruction and the data cache memories, the memory controllers and two SpaceWire interfaces. The processor, implemented in CMOS 65 nm technology, reaches an operational frequency of 120 MHz and area occupation of around 350 Kgates. The correlated Software Development Environment (SDE), with compiler, assembler, linker, debugger and instruction-level simulator, allows for an easy programming of the device in C language