Modeling and Control of Low side Active Clamp Forward Converter with Synchronous Rectification

Present work deals with the modeling and control of Low side Active Clamp Forward Converter with Synchronous rectification which is highly popular in telecommunication and point of use power supplies. The Forward converter is an isolated dc-dc buck converter and can provide wide range of output voltages based on the transformer turns ratio and duty cycle. The Forward converter is widely used as it provides galvanic isolation between input and output, simple, and gives high efficiency. The tertiary reset forward converter topology has limitation of duty cycle to 0.5 due to saturation and hard switching which causes voltage spikes during turn on and turn off of the MOSFET switch causing power loss. In order to overcome the saturation phenomena a clamp capacitor along with a MOSFET switch is connected in the primary to reset the transformer magnetizing inductance and ZVS phenomena takes place due to the resonance between the resonant inductance and resonant capacitance i.e., sum of the parasitic capacitance of the switches and transformer resulting in soft switching. In the secondary side of the forward converter the diodes are replaced with synchronous rectifiers resulting in low power loss. The steady state and transient analysis of the Low side Active Clamp Forward Converter topology with self-driven Synchronous Rectification has been analyzed in detail. The design of the topology was done and ZVS switching, reset of the transformer magnetizing inductance has been studied. The small signal modeling of the proposed converter topology under ideal conditions has been done and the control to output transfer function was derived using state space averaging model analysis. The PID controller is designed using frequency domain analysis to obtain . A single output voltage mode controlled Low side ACFC is designed and implemented in PSPIC