Mathematical Modelling of Source/Drain Extension Regions in SOI MOSFETs

Silicon-on-insulator has been used drastically in the CMOS technology due to its excellent properties. It has drastically reduced short channel effects. Also FD SOI MOSFET due to its superior scalability property than bulk MOSFET led to its extensive use in mixed-mode circuits. However, as we scale the device below the 65-nm t node, the devices face serious short channel effects in SOI MOSFETs in addition to other challenges. It seriously degrades analog figure of merit such as transconductance and cutoff frequency etc. There have been several proposed solution to this problem like laterally asymmetric-channel or graded-channel design. But in the case of nanoscale device, it is impossible to control the concentration profile at the source and the drain region. In the last few years, there have been several modeling approach to study these effects and propose a suitable model. However, the reduction in channel length have been the main problem. In case of bulk MOSFETs, charge sharing effects is negligible from Source/Drain regions due to better control of the active part of the device by the front gate. As now the thickness of the channel region is reduced to the order of 10 nm, it is difficult to fabricate the device and study the channel region without considering the effect of source/Drain doping gradient in the channel region. In the present work we have taken into account this effect and have effectively modeled the channel region to study the device in the weak inversion region