Novel Design for Dual Edge Triggered Flip-Flop for High Speed Low Power Application

In area of low power VLSI, switching activity of circuit node is of great concerned to reduce dynamic power. Dynamic power is directly proportional to switching activity of nodes. Switching activity vary according to input data pattern thereby for different input data sequence different power dissipation can occur. To achieve same data throughput as in single edged triggered flip-flop (SETFF), dual edged triggered flip-flop (DETFF) is an effective way to decrease power dissipation. DETFF reduces switching activity for same data throughput. In this paper, two different design of DETFF are investigated. The technique used to design DETFF is to generate pulse at every edge of clock to trigger data and/or latch stage of circuit. A conventional and a proposed design of DETFF are surveyed. Proposed DETFF utilized different scheme to generate pulse at every edge of clock. In view of power dissipation there is no considerable improvement but delay has been greatly reduced thereby overall PDP with respect to conventional DETF