International audienceThis work evaluates the SEE static and dynamic sensitivityof a single-chip many-core processor having implemented16 compute clusters, each one with 16 processing cores. The SEUerror-rate of an application implemented in the device is predictedby combining experimental results with those issued fromfault injection campaigns applying the CEU (Code EmulatingUpsets) approach. In addition, a comparison of the dynamic testswhen processing-cores cache memories are enabled and disabledis presented. The experiments were validated through radiationground testing performed with 14 MeV neutrons on the MPPA-256 many-core processor manufactured in TSMC CMOS 28HPtechnology. An analysis of the erroneous results in processorGPRs was ca...