We present a polynomial time algorithm for constructing a minimum completion time schedule of instructions from a basic block on RISC machines such as the Sun SPARC, the IBM 801, the Berkeley RISC machine, and the HP Precision Architecture. Our algorithm can be used as a heuristic for RISC processors with longer pipelines, for which there is no known optimal algorithm. Our algorithm can also handle time-critical instructions, which are instructions that have to be completed by a specific time. Time-critical instructions occur in some real-time computations, and can also be used to make shared resources such as registers quickly available for reuse. We also prove that in the absence of time-critical constraints, a greedy scheduling algorithm...
AbstractThe problem of minimizing the number of late tasks in the imprecise computation model is con...
[[abstract]]The problem of scheduling tasks, each of which is logically decomposed into a mandatory ...
The way the processes in a parallel program are scheduled on the processors of a multiprocessor syst...
We present a polynomial time algorithm for constructing a minimum completion time schedule of instru...
In this paper, We propose a faster algorithm for the following instruction scheduling problem: Give...
Instruction scheduling is central to achieving performance in modern processors with instruction lev...
Pipelining is a pervasive hardware implementation strategy used to increase the execution speeds of ...
Abstract Instruction scheduling is one of the most important steps for improving the performance of ...
In this paper, we consider the problem of scheduling a set of instructions on a single processor wit...
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT281-29021
Retiming, including pipelining, is applied to make the processing units (PUs) run at a required thro...
[[abstract]]Consideration is given to the problem of scheduling tasks each of which is logically dec...
Pipelining the functional units and memory interface of processors can result in shorter cycle times...
Modern superscalar architectures with dynamic scheduling and register renaming capabilities have int...
Anytime algorithms offer a tradeoff between computation time and the quality of the result returned....
AbstractThe problem of minimizing the number of late tasks in the imprecise computation model is con...
[[abstract]]The problem of scheduling tasks, each of which is logically decomposed into a mandatory ...
The way the processes in a parallel program are scheduled on the processors of a multiprocessor syst...
We present a polynomial time algorithm for constructing a minimum completion time schedule of instru...
In this paper, We propose a faster algorithm for the following instruction scheduling problem: Give...
Instruction scheduling is central to achieving performance in modern processors with instruction lev...
Pipelining is a pervasive hardware implementation strategy used to increase the execution speeds of ...
Abstract Instruction scheduling is one of the most important steps for improving the performance of ...
In this paper, we consider the problem of scheduling a set of instructions on a single processor wit...
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT281-29021
Retiming, including pipelining, is applied to make the processing units (PUs) run at a required thro...
[[abstract]]Consideration is given to the problem of scheduling tasks each of which is logically dec...
Pipelining the functional units and memory interface of processors can result in shorter cycle times...
Modern superscalar architectures with dynamic scheduling and register renaming capabilities have int...
Anytime algorithms offer a tradeoff between computation time and the quality of the result returned....
AbstractThe problem of minimizing the number of late tasks in the imprecise computation model is con...
[[abstract]]The problem of scheduling tasks, each of which is logically decomposed into a mandatory ...
The way the processes in a parallel program are scheduled on the processors of a multiprocessor syst...