High performance damascene metal gate MOSFETs for 0.1 um regime

Abstract—A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high di-electric constant gate insulators to MOSFET fabrication and mini-mize plasma damage to gate insulators. In this process, the gate in-sulators and gate electrodes are formed after ion implantation and high temperature annealing ( 1000 C) for source/drain forma-tion, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450 C. Furthermore, process-dam-ages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with Si