Abstract—In this paper, we report the design and implemen-tation of a reconfigurable system that exploits regional clocking resources that exist in Xilinx Virtex-4 FPGAs for increased performance and, for the first time, enhanced reliability. Unlike previous approaches, our system is able to individually manage the regional clock buffers (BUFRs) to adjust the frequency delivered to each hardware task and to detect and recover from faults affecting the clock-tree on-the-fly. Towards this end, we propose global and regional clock multiplexers, named GCMUX and RCMUX respectively, which allow for switching to spare clocking resources whenever needed. These multiplexers are based on the inner programmable interconnection points of the FPGA, lead...
a robust communication scheme between modules, it is possible to reduce the design effort of the glo...
Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock ...
FPGAs are increasingly being deployed in the cloud to accelerate diverse applications. They are to b...
Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous ...
opportunities for application design flexibility, enabling tasks to dynamically swap in and out of t...
AbstractIn order to obtain clocks needed for high speed, high-density designs, dedicated FPGA clock ...
In this thesis, methodology for partial self-reconfiguration of synchronous modules has been develop...
ABSTRACT FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. ...
This paper presents a simple clocking technique to migrate classical synchronous pipelined designs t...
Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that...
Field Programmable Gate Arrays (FPGAs) are now widely adopted as hardware accelerators due to their ...
This paper investigates the gains and losses in terms of power, area, reliability, and speed when ap...
As only the currently required functionality on a dynamic reconfigurable FPGA-based system is active...
The continuous scaling of microelectronics technology allows for keeping on increasing IC performanc...
The design space of FPGA-based processor systems is huge, because many parameters can be modified at...
a robust communication scheme between modules, it is possible to reduce the design effort of the glo...
Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock ...
FPGAs are increasingly being deployed in the cloud to accelerate diverse applications. They are to b...
Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous ...
opportunities for application design flexibility, enabling tasks to dynamically swap in and out of t...
AbstractIn order to obtain clocks needed for high speed, high-density designs, dedicated FPGA clock ...
In this thesis, methodology for partial self-reconfiguration of synchronous modules has been develop...
ABSTRACT FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. ...
This paper presents a simple clocking technique to migrate classical synchronous pipelined designs t...
Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that...
Field Programmable Gate Arrays (FPGAs) are now widely adopted as hardware accelerators due to their ...
This paper investigates the gains and losses in terms of power, area, reliability, and speed when ap...
As only the currently required functionality on a dynamic reconfigurable FPGA-based system is active...
The continuous scaling of microelectronics technology allows for keeping on increasing IC performanc...
The design space of FPGA-based processor systems is huge, because many parameters can be modified at...
a robust communication scheme between modules, it is possible to reduce the design effort of the glo...
Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock ...
FPGAs are increasingly being deployed in the cloud to accelerate diverse applications. They are to b...