Reducing EOT and Interface Trap Densities of High-k/III-V Gate Stacks

We report on in-situ surface preparation methods prior to atomic layer deposition (ALD) of gate dielectrics on In0.53Ga0.47As, and investigate their influence on the ability to scale the equivalent oxide thickness (EOT) and to reduce interface trap densities (Dit). The surface treatments employed here consist of in-situ cleaning involving alternating cycles of nitrogen plasma and trimethylaluminum (TMA) pulses prior to ALD of different dielectrics (1,2). We demonstrate metal-oxide-semiconductor capacitors with HfO2 dielectrics and low Dit (in the mid 1012 cm-2 eV-1 range) that can be scaled to sub-nm EOT. Accumulation capacitances exceed 3 µF/cm2 at 1 MHz on n-type In0.53Ga0.47As. Complementary studies of interface chemistry and surface morphology using transmission electron microscopy, x-ray photoelectron spectroscopy, and secondary ion mass spectrometry as a function of surface cleaning parameters are presented and elucidate the mechanisms by which these novel surface preparation methods allow for reducing both Dit and EOT